Renesas introduces new RISC-V CPU core with inclusion of various extensions

The Renesas processor core includes extensions that are aimed at improving performance while reducing code size. The company has reported a performance of 3.27 CoreMark/MHz, highlighting the potential for RISC-V to compete with established proprietary architectures in specific application scenarios.

“This achievement exemplifies how RISC-V ecosystem partners, such as Renesas, are rapidly advancing RISC-V innovation. Our RISC-V community now spans 70 countries with more than 4,000 members, and we eagerly anticipate further innovations emerging from this dynamic, expanding market,” says Calista Redmond, chief executive officer at RISC-V International.

Government bodies have implemented export restrictions on open-standard technologies, raising concerns about their impact on the RISC-V market. Nevertheless, Renesas’ latest development in RISC-V technology demonstrates the industry’s commitment towards innovating RISC-V based products, countering any potential setbacks caused by these restrictions.

Customization with new Renesas RISC-V core

RISC-V has gained widespread attention due to its modular approach, which allows the incorporation of various extensions aimed at improving specific functionalities. This feature has become a key highlight for the open standard technology, providing significant flexibility and optimization potential across diverse use cases. The idea of building a processor from the ground up while selectively adding extensions allows customers to strike a balance between power consumption, performance, and silicon area, ensuring efficient resource utilization.

Renesas has integrated several key extensions, including M, A, C, and B extensions. The M extension is focused on improving multiplication and division operations, featuring a hardware multiplier and divider unit for accelerating the execution speed for specific instructions. Meanwhile, the A extension provides support for atomic instructions, which are critical for managing concurrency and access control, particularly relevant in RTOS-based systems.

The C extension introduces compressed instructions that are encoded in 16-bits, effectively reducing memory space requirements for frequently used instructions. Finally, the B extension adds instructions specific to bit manipulation, which is important for handling peripheral registers, protocols, and data structures.

There’s more to the Renesas processor core

Renesas has enhanced the efficiency and debugging capabilities of application software through the introduction of a stack monitor register, which helps in the detection and prevention of stack memory overflows.

The Renesas CPU core incorporates a dynamic branch prediction unit to handle complexity more effectively. This unit continuously observes code behavior and dynamically predicts the next instruction likely to be executed. In the field of system development, robust debugging capabilities are crucial, and Renesas’ CPU core supports a compact two-wire JTAG debug interface in addition to the standard JTAG interface.

To reduce latency, Renesas has implemented a register bank save function, which streamlines the backup and restoration of the CPU working registers. Renesas believes that in embedded devices, particularly those operating at the microcontroller level, maintaining hard real-time behavior is essential to ensure the system responds to events within a predetermined time frame.

Elsewhere, Renesas has recently announced its strategy to develop advancements in the next generation automotive systems, with its product lineup including R-Car SoC and automotive microcontrollers based on the Arm architecture. Additionally, the company is actively pursuing the acquisition of Sequans Communications, a move aimed at broadening its portfolio within the IoT domain.

Article Topics

CPU  |  Renesas  |  RISC-V  |  System-on-Chips