Agile Analog unveils chip tech for RISC-V in battery-powered IoT systems
Agile Analog showcased an analog IP subsystem at the RISC-V Summit Europe designed for RISC-V-based applications that require a battery power supply. The subsystem comprises a power management unit, a sleep management unit, and data converters. These building blocks form the essential components of a system-on-chip (SoC) design that are used in increasingly sophisticated IoT applications.
Agile Analog confirms that the new analog IP subsystem works in analog and digital environments. Among the main benefits: manufacturers can reduce the cost of devices since fewer components are needed.
According to Agile Analog, design and verification processes have become more complex due to the challenge of integrating analog IP blocks from different vendors. The analog IP system aims to simplify and streamline the chip design process by providing a customizable and process-agnostic analog IP subsystem that can efficiently integrate with digital IPs from other RISC-V developers.
“The RISC-V architecture is enabling a surge of new SoC product developments, and the demand for more accessible and configurable IP solutions is increasing. One of the major challenges that digital chip designers face is in integrating the analog circuitry to support their SoC designs,” says Chris Morrison, the director of product marketing at Agile Analog.
Agile Analog has developed an analog IP subsystem in the SystemVerilog model, enabling chip designers to integrate it into their existing SoC digital verification setup. The subsystem can also connect directly to the microcontroller’s peripheral bus.
“RISC-V is already seen in over 10 billion cores globally, and the ecosystem is flourishing. It’s really important that there are innovative solutions like this to help chip designers in our community to fast-track the delivery of exciting new RISC-V IoT applications,” says Calista Redmond, the chief executive officer of RISC-V International.
Why do we need an analog IP subsystem for SoC design?
Agile Analog defines analog IP as the on-chip system responsible for managing external connections, power management, and other analog functions. This includes features such as voltage regulators and oscillators. The company bases its value proposition on every chip needing analog IP, as even digital interfaces such as SerDes require mainly analog IP.
Incorporating analog IP into the primary SoC design helps reduce overall system costs. It simplifies the process, resulting in improved efficiency. According to Agile Analog, using analog components instead of separate discrete devices can significantly reduce costs. This cost reduction can often be up to 10 times, resulting in overall savings for the system.
The company thinks that analog IP can help with supply chain logistics. They believe that dealing with external sourcing, procurement and management components can be difficult and take up a lot of time. The use of analog IP reduces the number of external components, which simplifies supply chain logistics.
“With our RISC-V analog IP subsystem, it’s possible to access the appropriate analog IP for a specific process and foundry. This can then be integrated seamlessly with digital IP from a digital IP provider in the RISC-V space, simplifying chip design and accelerating the time to market for new RISC-V IoT applications,” Morrison adds.
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Article Topics
Agile Analog | chip | design | IoT | power consumption | RISC-V
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